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大家好！我创建了SHDL（简单硬件描述语言），这是一个将硬件描述简化到绝对基础的实验。在SHDL中，没有算术运算符，没有隐式位宽，也没有高级结构。你需要从逻辑门和导线显式构建一切，然后以层次化的方式组合更大的组件。这个目标不是合成或性能，而是理解：当抽象被去除时，数字系统实际上是什么样子的。SHDL配有PySHDL，这是一个Python接口，允许你加载电路、输入信号、逐步模拟并观察输出。在底层，SHDL将电路编译为C语言以实现快速执行，但语言本身保持故意简小和透明。这并不是为了取代Verilog或VHDL。它的目标是：- 从基本原理学习数字逻辑- 实验硬件描述语言和语言设计- 教授或可视化复杂硬件如何从简单门电路中产生我特别希望能收到关于以下方面的反馈：- 语言设计选择- 哪些感觉不必要的限制与教育价值- 这种“反抽象”硬件描述语言对你是否有用代码库： https://github.com/rafa-rrayes/SHDLPython包：PySHDL在PyPI上感谢阅读，我非常欢迎批评意见。

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Hi, everyone!I built SHDL (Simple Hardware Description Language) as an experiment in stripping hardware description down to its absolute fundamentals.In SHDL, there are no arithmetic operators, no implicit bit widths, and no high-level constructs. You build everything explicitly from logic gates and wires, and then compose larger components hierarchically. The goal is not synthesis or performance, but understanding: what digital systems actually look like when abstractions are removed.SHDL is accompanied by PySHDL, a Python interface that lets you load circuits, poke inputs, step the simulation, and observe outputs. Under the hood, SHDL compiles circuits to C for fast execution, but the language itself remains intentionally small and transparent.This is not meant to replace Verilog or VHDL. It’s aimed at:- learning digital logic from first principles- experimenting with HDL and language design- teaching or visualizing how complex hardware emerges from simple gatesI would especially appreciate feedback on:- the language design choices- what feels unnecessarily restrictive vs. educationally valuable- whether this kind of “anti-abstraction” HDL is useful to youRepo: https://github.com/rafa-rrayes/SHDLPython package: PySHDL on PyPIThanks for reading, and I’m very open to critique.

SHDL – 一种基于逻辑门的最小硬件描述语言